关键词: 预提升技术, 非一致高速缓存结构, 任意步长, 访存模式, 预取技术

Abstract: Along with the development of microelectronics, the researches of on-chip non-uniform caches become more and more popular. A technique which can recognize data with the arbitrary stride access patterns and pre-promote them to cache banks adjacent with processors is proposed. Besides detailing the design of the arbitrary-stride pre-promotion, pre-promotion is compared with pre-fetching, and a combination of them in one cache system is proposed. All techniques are evaluated by testing 11 benchmarks from NPB (NAS parallel benchmark) and SPEC 2000 in a full-system simulator. The experimental results show that the IPC (instructions per cycle) of the processor with pre-promotion is increased by 4.17% averagely when the reference prediction table achieves 16 entries size and by 4.91% averagely when it arrives at 32 entries size. After combining pre-promotion and pre-fetching, the IPC is increased by 8.84% and 11.06% respectively.

Key words: pre-promotion, non-uniform cache architecture, arbitrary stride, access pattern, pre-fetching