关键词: 去块滤波, 有向无环图集, 并行处理, 多核平台, 通用并行计算架构

Abstract: For the deblocking filter of high efficiency video coding (HEVC), current literatures lack the in-depth research on the cross-layer parallel implementation between algorithm layer and platform layer. Based on the directed acyclic graph set (DAGS) at algorithm layer and the compute unified device architecture (CUDA) at platform layer, this paper proposes a cross-layer parallel decoding scheme for HEVC deblocking filter. The proposed scheme exploits the independent pixel regions to reduce cache accesses, and weakens the sequential dependence of filtering process to facilitate the parallel optimization. By evaluating three implementation schemes of HEVC deblocking filter: “serial”, “DAGS+multi-core CPU” and “DAGS+GPU”, the experimental results demonstrate that the proposed “DAGS+GPU” scheme can achieve the speedup as high as 11~24 times, and thus significantly save the decoding time while maintaining similar rate-distortion performance.

Key words: deblocking filter, directed acyclic graph set, parallel processing, multi-core platform, compute unified device architecture