关键词: 三维片上网络（3D NoC）, 通信瓶颈, 拓扑结构, 拓扑结构分类

Abstract: Three-dimensional network on chip (3D NoC) is developed based on three-dimensional integrated circuit (3D IC), system on chip (SoC) and two-dimensional network on chip (2D NoC). 3D NoC is mainly used to solve the problems such as communication bottleneck of highly integrated chips. It has attracted great attention from both academia and industry at home and abroad. 3D NoC topology structure reflects the layout and connectivity of communications node in the chip, which is crucial for the performance of 3D chip. This paper introduces 2D NoC, the evolution from 2D NoC to 3D NoC, the advantages and problems of adopting 3D NoC and the key technical issues which can be solved by 3D NoC, and analyzes the overall development of 3D NoC. 3D topology is one of the key problems in the design of 3D NoC. This paper mainly studies the different classification methods for 3D NoC topology and divides 3D NoC topologies into 9 categories in terms of communication, then gives a thorough study of 3D NoC topology structures with comparison and analysis of the characteristics for each topology structure. Finally, this paper indicates the possible future research development of 3D NoC topology.

Key words: three-dimensional network on chip (3D NoC), communication bottleneck, topology, classification of topology