关键词: 无线片上网络, 拓扑结构, 路由算法, 无线链路放置, 平均延迟, 总功耗

Abstract: Traditional network-on-chip (NoC) uses metal links to connect routing nodes. The increase in IP cores on the chip not only leads to an increase in wiring complexity, but also leads to an increase in NoC transmission delay and power consumption. Due to the successful development of the micro antenna on the chip, the wireless com-munication within the chip is realized. Wireless communication has the characteristics of high bandwidth, low latency, and low power consumption, making the wireless network-on-chip (WNoC) an ideal alternative to traditional NoC, which can significantly improve system performance. Aiming at solving the problem of high energy consumption and delay caused by multi-hop communication between remote cores in the traditional large-scale network, this paper proposes an [8×8×4] 3D hybrid wireless network-on-chip architecture and a routing algorithm for this architecture. In addition, the problem of wireless node and wireless link placement in the topology design of hybrid WNoC has been discussed. The simulation results show that the deployment of wireless nodes in layer 0 and 3 has the best performance. Compared with the traditional network-on-chip structure, the topology proposed in this paper has greatly improved the average network delay and the total network power consumption.

Key words: wireless network-on-chip, topology, routing algorithm, wireless link placement, average delay, total power consumption