关键词: 硬件加速器, 现场可编程门阵列（FPGA）, 卷积神经网络（CNN）, 高层次综合

Abstract: At present, convolutional neural network (CNN) has been widely used in image classification, object detection and other computer vision fields. However, in the forward inference stage, many practical applications often have low latency and strict power constraints. To solve this problem, an FPGA (field-programmable gate array) accelerator of CNN with the single instruction multiple data (SIMD) structure is designed and implemented using the optimization strategies such as parameter reordering and multi-channel data transmission. Taking YOLOv2 object detection algorithm as an example, the whole process of mapping CNN model to FPGA is described. The performance and resources of the accelerator are analyzed and modeled with the actual transmission delay being taken into account. It reduces the error between the theoretical and the actual delay of the accelerator. At the same time, the input and output modules in the accelerator are improved, which effectively improves the actual utilization of bus bandwidth. The experimental results show that a performance of 30.15 GOP/s is obtained on the Zedboard. Compared with the Xeon E5-2620 v4 CPU, 120.4 times of energy efficiency and 7.3 times of performance are obtained, and compared with the dual-core ARM-A9 CPU, 86 times of energy efficiency and 112.9 times of performance respectively are obtained.

Key words: hardware accelerator, field-programmable gate array (FPGA), convolutional neural network (CNN), high-level synthesis