关键词: 片状多核处理器, 模拟器, 互联结构, 数据一致性

Abstract: Traditional bus sharing multi-processor chips meet bottleneck trouble with the number of processor cores increasing. In the structure design of novel Tiled CMP(chip multi-processor), onchip interconnection shows great impact on platform scalability and performance. Implementation of low latency and high bandwidth onchip routing structure becomes current hotspot. Execute-driven SimTile is implemented by a structure of Tiled 16-core CMP de-sign, which can offer flexible configuration and full-functional CMP building models. The simulator supports effi-cient global shared cache hierarchy and high performance onchip routing structure. Modules configuration is adopted to setup the platform parameters, such as processor numbers, interconnection network topology, cache co-herence protocols, global registers communication and the storage hierarchy etc. The simulator has been evaluated to have fine efficiency in Tiled CMP simulation as to provide a novel flexible and well scalable platform.

Key words: Tiled CMP(chip multi-processor), simulator, interconnection, coherence