关键词: 三维片上网络, 异构布局, 超图划分, hMetis

Abstract: Network-on-chip (NoC) is a feasible technology with a large number of embedded cores integrated into a single wafer. Compared with the traditional system-on-chip, it can better meet the challenges of the future need for more large-scale integration of the kernel, resulting in a wider range of applications. However, most of the research is based on homogeneous architecture assuming that all the tiles have the same area. But this assumption is not realistic. Therefore, the research on heterogeneous 3D NoCs is very necessary. With heterogeneous 3D NoCs, a reasonable division of network elements has a significant impact on the performance of heterogeneous 3D NoCs. This paper firstly describes the floorplanning based on 3D NoC of heterogeneous network architecture, and maps VLSI (very large scale  integration) into a hyper-graph, then divides the hyper-graph into multi-levels. Secondly, this paper introduces varivarious of common algorithms in the different phases, analyzes the potential problems of the algorithms, and puts forward several new algorithms to improve the performance of NoC. Finally, a number of simulation experiments are conducted based on a few conventional VLSI data sets to compare the performance of the different phases with different algorithms and choose the best hMetis algorithm framework on the data sets.

Key words: 3D network-on-chip, heterogeneous floorplanning, hyper-graph partition, hMetis