计算机科学与探索 ›› 2017, Vol. 11 ›› Issue (8): 1224-1234.DOI: 10.3778/j.issn.1673-9418.1701043

• 学术研究 • 上一篇    下一篇

多核共享资源冲突延迟上限优化方法

张吉赞1,苑雅娟2+   

  1. 1. 北京理工大学 计算机科学与技术学院,北京 100081
    2. 沧州医学高等专科学校,河北 沧州 061001
  • 出版日期:2017-08-01 发布日期:2017-08-09

Optimization of Upper Bound of Interference Delay in Multicore

ZHANG Jizan1, YUAN Yajuan2+   

  1. 1. School of Computer Science and Technology, Beijing Institute of Technology, Beijing 100081, China
    2. Cangzhou Medical College, Cangzhou, Hebei 061001, China
  • Online:2017-08-01 Published:2017-08-09

摘要: 嵌入式多核结构的共享资源冲突是硬实时任务最差情况执行时间(worst-case execution time,WCET)估算的难点,而且通过减少共享资源冲突延迟的估算可以减少硬实时任务的WCET估算值,提高硬实时任务的可调度性。针对带有冲突感知总线(interference-aware bus arbiter,IABA)的嵌入式多核结构,提出了一种基于bank-column缓存划分的访存请求冲突延迟上限优化方法,根据bank冲突次数和冲突延迟上限的关系,该方法通过优化bank到核映射来减少bank冲突发生次数,从而减小冲突延迟上限和WCET估算值。实验结果表明,与现有冲突延迟上限界定方法相比,提出的方法能减少约29%的WCET估算值。

关键词: 多核结构, 硬实时任务, bank冲突, bank-column划分, bank到核映射

Abstract:  The inter-task interferences on the shared resources of embedded multicore are the difficulty for the WCET (worst-case execution time) estimation of hard real-time tasks. Moreover, the decrease of the delay caused by the interferences on the shared resources can reduce the estimated WCET and improve the schedulability of hard real-time tasks. This paper proposes an optimization method to reduce the upper bound of inter-task interference    delay in the multicore with interference-aware bus arbiter (IABA). According to the relationship between the upper bound of inter-task interference delay and the count of bank conflict, this paper optimizes bank to core mapping to reduce the count of bank conflict, and then reduces the upper bound of inter-task interference delay and the estimated WCET. Compared with existing methods, the proposed method can reduce about 29% of the estimated WCET.

Key words: multicore, hard real-time task, bank conflict, bank-column partitioning, bank to core mapping