Using HLS to Develop FPGA Heterogeneous Acceleration System: Problems, Optimization Methods and Opportunities

doi:10.3778/j.issn.1673-9418.2210102

Abstract

Abstract: Currently, field programmable gate arrays (FPGAs) are favored by both academia and industry due to their programmability and excellent energy efficiency ratio. However, traditional FPGA development based on hardware description languages faces programming challenges. Hardware description languages, which are different from commonly used high-level languages, hinder software developers from utilizing FPGAs. High-level synthesis (HLS) enables developers to directly develop FPGA hardware from high-level languages such as C/C++, and is widely regarded as the preferred solution to this problem. In recent years, there have been many works in academia on HLS, dedicated to solving various problems in the HLS application process and improving the performance of systems developed through HLS. This paper lists feasible optimization directions from the perspective of heterogeneous system developers around the issue of developing FPGA heterogeneous systems using HLS. At the compilation optimization level, HLS tools can automatically generate high-performance RTL designs by inserting compilation guidance and designing efficient spatial exploration algorithms. At the memory access optimization level, HLS tools can set up buffers, split and replicate data to improve the overall system bandwidth. At the parallel optimization level, HLS tools can implement statement-level, task-level and board-level parallelism. Meanwhile, some technologies such as DSL, although they cannot directly improve the performance of heterogeneous acceleration systems, can further enhance the usability of HLS tools. Finally, this paper summarizes some challenges currently faced by HLS and prospects the future research on HLS.

Key words: field programmable gate array (FPGA), high-level synthesis (HLS), heterogeneous system, high-level language, compiling optimization

摘要： 目前，现场可编程门阵列（field programmable gate array，FPGA）由于可编程性与出色的能效比受到了学术界与工业界的青睐，但是传统的基于硬件描述语言的FPGA开发方式面临编程挑战。硬件描述语言区别于通常使用的高级语言，阻碍了软件开发者对FPGA的利用。高层次综合（high-level synthesis，HLS）使得开发者可以从高级语言如C/C++层面直接进行FPGA硬件层面的开发，是解决这一问题的首选，受到了广泛的关注。近年来，学术界有许多关于HLS的工作，致力于解决HLS应用过程中的各类问题，并提升通过HLS开发的系统的性能。围绕使用HLS开发FPGA异构系统这一问题，以一种异构系统开发者的视角，列举了可行的优化方向。在编译优化层面，HLS工具可以通过插入编译指导与设计高效的空间探索算法，自动生成性能较高的RTL设计；在访存优化层面，HLS工具可以设立缓冲区，拆分并复制数据，以提升系统整体带宽；在并行优化层面，HLS工具可以实现语句级、任务级以及板卡级的并行。一些如DSL的技术虽然不能直接提升异构加速系统的性能，但是可以进一步提升HLS工具的可用性。最后，总结了当前HLS面临的一些挑战，并对HLS的未来研究方向进行了展望。

关键词: 现场可编程门阵列（FPGA）, 高层次综合, 异构系统, 高级语言, 编译优化

XU Cheng, GUO Jinyang, LI Chao, WANG Jing, WANG Taolei, ZHAO Jieru. Using HLS to Develop FPGA Heterogeneous Acceleration System: Problems, Optimization Methods and Opportunities[J]. Journal of Frontiers of Computer Science and Technology, 2023, 17(8): 1729-1748.

徐诚, 郭进阳, 李超, 王靖, 汪陶磊, 赵杰茹. 使用HLS开发FPGA异构加速系统：问题、优化方法和机遇[J]. 计算机科学与探索, 2023, 17(8): 1729-1748.

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