Abstract: Along with the development of microelectronics, the researches of on-chip non-uniform caches become more and more popular. A technique which can recognize data with the arbitrary stride access patterns and pre-promote them to cache banks adjacent with processors is proposed. Besides detailing the design of the arbitrary-stride pre-promotion, pre-promotion is compared with pre-fetching, and a combination of them in one cache system is proposed. All techniques are evaluated by testing 11 benchmarks from NPB (NAS parallel benchmark) and SPEC 2000 in a full-system simulator. The experimental results show that the IPC (instructions per cycle) of the processor with pre-promotion is increased by 4.17% averagely when the reference prediction table achieves 16 entries size and by 4.91% averagely when it arrives at 32 entries size. After combining pre-promotion and pre-fetching, the IPC is increased by 8.84% and 11.06% respectively.

Key words: pre-promotion, non-uniform cache architecture, arbitrary stride, access pattern, pre-fetching

摘要： 随着微电子工艺的不断进步, 片上大容量非一致cache 的研究受到广泛关注。提出了一种面向非一致cache 的任意步长预提升技术, 它能够优化非一致cache 中的数据组织, 使得即将访问的数据被放置在距离处理器较近的cache bank 中, 从而降低访存延迟, 提升系统性能。详细介绍了任意步长预提升技术的设计, 比较了预提升技术与预取技术的差别, 并提出了二者的结合技术。通过对来自NPB 和SPEC 2000 的11个基准测试程序在全系统模拟器上的实验评测, 发现任意步长预提升技术能够有效减小访存延迟, 在访存预测表尺寸为16 和32 的情况下, 系统IPC 分别平均增长4.17%和4.91%; 在结合预提升和预取技术的情况下, 系统IPC 分别平均增长8.84%和11.06%。

关键词: 预提升技术, 非一致高速缓存结构, 任意步长, 访存模式, 预取技术