Parallel Architecture Design for OpenVX Kernel Image Processing Functions

doi:10.3778/j.issn.1673-9418.2012085

Journal of Frontiers of Computer Science and Technology ›› 2022, Vol. 16 ›› Issue (7): 1570-1582.DOI: 10.3778/j.issn.1673-9418.2012085

• High Performance Computing • Previous Articles Next Articles

Parallel Architecture Design for OpenVX Kernel Image Processing Functions

PAN Fengrui¹^,⁺(), LI Tao¹^,², XING Lidong¹, ZHANG Haocong¹, WU Guanzhong¹

1. School of Electronic Engineering, Xi’an University of Posts & Telecommunications, Xi’an 710121, China
2. School of Computer Science & Technology, Xi’an University of Posts & Telecommunications, Xi’an 710121, China

Received:2020-12-22 Revised:2021-02-25 Online:2022-07-01 Published:2021-03-23
Supported by:
the Science and Technology Overall Planning Project of Shaanxi Province(2015KTCQ013);the Project of Collaborative Innovation Center of Shaanxi Provincial Department of Education(17JF032);the Scie.pngic Research Project of Shaanxi Provincial Department of Education(20JY058)

面向OpenVX核心图像处理函数的并行架构设计

潘风蕊¹^,⁺(), 李涛¹^,², 邢立冬¹, 张好聪¹, 吴冠中¹

1.西安邮电大学电子工程学院,西安 710121
2.西安邮电大学计算机学院,西安 710121

作者简介:潘风蕊（1996—）,女,陕西渭南人,硕士研究生,主要研究方向为集成电路系统设计。
PAN Fengrui, born in 1996, M.S. candidate. Her research interest is integrated circuit system design.
李涛（1954—）,男,北京人,博士,教授,CCF会员,主要研究方向为计算机体系结构、计算机图形学、大规模集成电路等。
LI Tao, born in 1954, Ph.D., professor, member of CCF. His research interests include computer architecture, computer graphics, large-scale integrated circuit, etc.
邢立冬（1980—）,男,山东人,博士,高级工程师,CCF会员,主要研究方向为集成电路系统设计。
XING Lidong, born in 1980, Ph.D., senior engineer, member of CCF. His research interest is integrated circuit system design.
张好聪（1996—）,女,陕西渭南人,硕士研究生,主要研究方向为集成电路系统设计。
ZHANG Haocong, born in 1996, M.S. candidate. Her research interest is integrated circuit system design.
吴冠中（1995—）,男,陕西西安人,硕士研究生,主要研究方向为集成电路系统设计。
WU Guanzhong, born in 1995, M.S. candidate. His research interest is integrated circuit system design.
基金资助:
陕西省科技统筹项目(2015KTCQ013);陕西省教育厅协同创新中心项目(17JF032);陕西省教育厅科研计划项目(20JY058)

Abstract

Abstract:

Although the traditional programmable processors are highly flexible, their processing speed and perfor-mance are inferior to the application specific integrated circuit (ASIC). Image processing is often a diverse, intensive and repetitive operation, so the processor must balance speed, performance and flexibility. OpenVX is an open source standard for preprocessing or auxiliary processing of image processing, graph computing and deep learning applications. Aiming at the kernel visual function library of OpenVX 1.3 standard, this paper designs and implements a programmable and extensible OpenVX parallel processor. The architecture adopts an application specific instruction processor (ASIP). After analyzing and comparing the topological characteristics of various interconnection networks, the backbone of the ASIP chooses the hierarchically cross-connected Mesh+ (HCCM+) with outstanding performance, and processing element (PE) is set at network nodes. PE array is constructed to support dynamic configuration, and a parallel processor is designed to realize programmable image processing based on efficient routing and com-munication. The proposed architecture is suitable for data parallel computing and emerging graph computing. The two computing modes can be configured separately or mixed. The kernel visual function and graph computing model are mapped to the parallel processor respectively to verify the two modes and compare the image processing speed under different PE numbers. The results show that OpenVX parallel processor can complete the mapping and linear speedup of kernel functions and high complexity graph calculation model. The average speedup of scheduling 16 PEs to various functions is approximately 15.0375. When implemented on an FPGA board with a 20 nm XCVU440 device, the prototype can run at a frequency of 125 MHz.

Key words: OpenVX kernel image processing functions, application specific instruction processor (ASIP), parallel processor, hierarchically cross-connected mesh+ (HCCM+), graph calculation model

摘要：

传统的可编程处理器虽然高度灵活,但其处理速度及性能不及专用集成电路（ASIC）,而图像处理往往是多样、密集且重复的操作,因此处理器要兼顾速度、性能及灵活性。OpenVX是图像图形处理、图计算和深度学习等应用的预处理或者辅助处理开源标准,基于最新的OpenVX 1.3标准中的核心图像处理函数库,设计并实现了一种可编程、可扩展的专用指令集处理器（ASIP）——OpenVX并行处理器。首先分析对比了各种互联网络的拓扑特性,选择了性能比较突出的层次交叉互联网络（HCCM+）作为系统主干,在网络节点处设置处理单元（PE）构成支持动态配置的4×4 PE阵列,结合高效的路由通信方式设计了并行处理器,实现可编程的图像处理。其次所提出的架构适合数据并行计算和新兴的图计算,两种计算模式可单独或混合配置使用,分别将核心视觉函数及图计算模型映射到并行处理器上对两种模式进行验证,对比PE数目不同的情况下图像处理的速度。实验结果表明,并行处理器能够完成对基本核心函数和高复杂度的图计算模型的映射,在数据并行计算和流水线处理两种模式下,可以对图像处理线性加速,调用16个PE对各类函数的平均加速比可达15.037 5。验证环境采用20 nm XCVU440平台芯片,综合实现后频率为125 MHz。

关键词: OpenVX核心图像处理函数, 专用指令集处理器（ASIP）, 并行处理器, 层次交叉互联网络（HCCM+）, 图计算模型

CLC Number:

TP302

PAN Fengrui, LI Tao, XING Lidong, ZHANG Haocong, WU Guanzhong. Parallel Architecture Design for OpenVX Kernel Image Processing Functions[J]. Journal of Frontiers of Computer Science and Technology, 2022, 16(7): 1570-1582.

潘风蕊, 李涛, 邢立冬, 张好聪, 吴冠中. 面向OpenVX核心图像处理函数的并行架构设计[J]. 计算机科学与探索, 2022, 16(7): 1570-1582.

Figures/Tables 27

Fig.1 OpenVX graph calculation model

Fig.2 Interconnection network topology

Table 1 Comparison of network topology performance

类型	Mesh	HCCM	HCCM-	HCCM+
级数	$n$	$n$	$n$	$n$
边长	$2 n$	$2 n$	$2 n$	$2 n$
节点数	$2 2 n$	$2 2 n$	$2 2 n$	$2 2 n$
边数	$2 2 n + 1 - 2 n + 1$	$(5 / 2) 4 n - 2 n + 1$	$2 (4 n - 1)$	$(8 / 3) 4 n - 2 n + 1 - (2 / 3)$
直径	$2 n + 1 - 2$	$3 × 2 n - 1 - 2$	$2 n - 1$	$2 n - 1$
等分宽度	$2 n$	$2 n$	4	$2 n + 2$

Table 1 Comparison of network topology performance

类型	Mesh	HCCM	HCCM-	HCCM+
级数	$n$	$n$	$n$	$n$
边长	$2 n$	$2 n$	$2 n$	$2 n$
节点数	$2 2 n$	$2 2 n$	$2 2 n$	$2 2 n$
边数	$2 2 n + 1 - 2 n + 1$	$(5 / 2) 4 n - 2 n + 1$	$2 (4 n - 1)$	$(8 / 3) 4 n - 2 n + 1 - (2 / 3)$
直径	$2 n + 1 - 2$	$3 × 2 n - 1 - 2$	$2 n - 1$	$2 n - 1$
等分宽度	$2 n$	$2 n$	4	$2 n + 2$

Fig.3 OpenVX parallel processor architecture

Fig.4 PE architecture

Fig.5 ALU0 I/O data path

Fig.6 Global control circuit

Fig.7 Route structure

Fig.8 Data routing between PEs

Fig.9 Data parallel computing pattern mapping

Fig.10 Image segmentation in data parallel computing mode

Fig.11 Morphological filtering execution flow

Fig.12 Pipeline processing pattern mapping

Fig.13 Morphological filtering data segmentation

Fig.14 Simulation test platform

Table 2 Comparison of speedups of basic kernel functions

函数类别		$T & S u p$	1PE	2PE	4PE	8PE	16PE
Ⅰ	通道提取	T/clk	307 364	167 045	90 667	44 740	20 382
	通道提取	$S u p$	1.00	1.81	3.45	6.94	15.29
	颜色转换	T/clk	307 375	169 820	89 094	44 290	20 103
	颜色转换	$S u p$	1.00	1.84	3.39	6.87	15.08
	位深转换	T/clk	307 372	171 716	90 403	44 871	20 301
	位深转换	$S u p$	1.00	1.79	3.40	6.85	15.14
Ⅱ	直方图	T/clk	614 426	372 379	187 897	94 818	41 375
	直方图	$S u p$	1.00	1.65	3.27	6.48	14.85
	图像积分	T/clk	438 723	270 816	141 068	68 981	29 643
	图像积分	$S u p$	1.00	1.62	3.11	6.36	14.80
Ⅲ	中值滤波	T/clk	307 283	167 914	85 594	44 858	20 162
	中值滤波	$S u p$	1.00	1.83	3.57	6.85	15.21
	图像膨胀	T/clk	307 282	167 001	85 832	44 990	20 162
	图像膨胀	$S u p$	1.00	1.79	3.52	7.34	15.24
	图像腐蚀	T/clk	307 282	167 001	85 832	44 924	20 162
	图像腐蚀	$S u p$	1.00	1.79	3.52	7.34	15.24
	Sobel	T/clk	307 285	168 837	86 074	44 924	20 256
	Sobel	$S u p$	1.00	1.82	3.59	7.12	15.17
Ⅳ	Canny	T/clk	307 314	187 386	91 735	46 775	20 750
	Canny	$S u p$	1.00	1.64	3.35	6.57	14.81
	高斯金字塔	T/clk	409 615	245 278	121 547	62 824	27 695
	高斯金字塔	$S u p$	1.00	1.67	3.37	6.52	14.79
	Harris Corner	T/clk	307 309	182 922	89 856	46 917	20 722
	Harris Corner	$S u p$	1.00	1.68	3.42	6.55	14.83

Table 2 Comparison of speedups of basic kernel functions

函数类别		$T & S u p$	1PE	2PE	4PE	8PE	16PE
Ⅰ	通道提取	T/clk	307 364	167 045	90 667	44 740	20 382
	通道提取	$S u p$	1.00	1.81	3.45	6.94	15.29
	颜色转换	T/clk	307 375	169 820	89 094	44 290	20 103
	颜色转换	$S u p$	1.00	1.84	3.39	6.87	15.08
	位深转换	T/clk	307 372	171 716	90 403	44 871	20 301
	位深转换	$S u p$	1.00	1.79	3.40	6.85	15.14
Ⅱ	直方图	T/clk	614 426	372 379	187 897	94 818	41 375
	直方图	$S u p$	1.00	1.65	3.27	6.48	14.85
	图像积分	T/clk	438 723	270 816	141 068	68 981	29 643
	图像积分	$S u p$	1.00	1.62	3.11	6.36	14.80
Ⅲ	中值滤波	T/clk	307 283	167 914	85 594	44 858	20 162
	中值滤波	$S u p$	1.00	1.83	3.57	6.85	15.21
	图像膨胀	T/clk	307 282	167 001	85 832	44 990	20 162
	图像膨胀	$S u p$	1.00	1.79	3.52	7.34	15.24
	图像腐蚀	T/clk	307 282	167 001	85 832	44 924	20 162
	图像腐蚀	$S u p$	1.00	1.79	3.52	7.34	15.24
	Sobel	T/clk	307 285	168 837	86 074	44 924	20 256
	Sobel	$S u p$	1.00	1.82	3.59	7.12	15.17
Ⅳ	Canny	T/clk	307 314	187 386	91 735	46 775	20 750
	Canny	$S u p$	1.00	1.64	3.35	6.57	14.81
	高斯金字塔	T/clk	409 615	245 278	121 547	62 824	27 695
	高斯金字塔	$S u p$	1.00	1.67	3.37	6.52	14.79
	Harris Corner	T/clk	307 309	182 922	89 856	46 917	20 722
	Harris Corner	$S u p$	1.00	1.68	3.42	6.55	14.83

Fig.15 Weight comparison of different functions serial parallelism ratio

Fig.16 Comparison of processing time of different functions

Fig.17 Contrast before and after image processing

Fig.18 Graph pipeline processing

Table 3 Processing time of different number of pipelines

流水线数目/个	处理时间/clk
1	313 045
2	220 454
3	132 086
4	92 072

Fig.19 Graph execution model acceleration ratio

Fig.20 Average delay comparison

Fig.21 Throughput comparison

Fig.22 Speedup comparison of kernel functions

Table 4 Comparison of processing time

比较项	FPGA型号	PE数目	处理时间/ms
本文	XCVU440-flga2892-2-e	1	2.46
		2	1.35
		4	0.69
		8	0.36
		16	0.16
文献[18]	XC3S2000	—	0.66
文献[19]	EP1K30TC144-1	—	6.30
文献[20]	CYCLONEEP1C20	—	1.30

Table 5 Performance comparison

比较项	LUT(look up table)	FF(filp flop)	Slice	频率/MHz	支持处理类型
本文	28 768	8 704	1 596	125	38
文献[18]	1 289	1 458	1 130	105	1
文献[19]	—	—	—	80	1
文献[20]	4 096	—	—	50	1

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Parallel Architecture Design for OpenVX Kernel Image Processing Functions

面向OpenVX核心图像处理函数的并行架构设计

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