Parallel Implementation of OpenVX Feature Extraction Functions in Programmable Processing Architecture

doi:10.3778/j.issn.1673-9418.2012080

Journal of Frontiers of Computer Science and Technology ›› 2022, Vol. 16 ›› Issue (7): 1583-1593.DOI: 10.3778/j.issn.1673-9418.2012080

• High Performance Computing • Previous Articles Next Articles

Parallel Implementation of OpenVX Feature Extraction Functions in Programmable Processing Architecture

ZHANG Haocong¹^,⁺(), LI Tao¹^,², XING Lidong¹, PAN Fengrui¹

1. School of Electronic Engineering, Xi’an University of Posts & Telecommunications, Xi’an 710121, China
2. School of Computer Science & Technology, Xi’an University of Posts & Telecommunications, Xi’an 710121, China

Received:2020-12-21 Revised:2021-02-25 Online:2022-07-01 Published:2021-03-23
Supported by:
the Science and Technology Overall Planning Project of Shaanxi Province(2015KTCQ013);the Project of Collaborative Innovation Center of Shaanxi Provincial Department of Education(17JF032);the Scie.pngic Research Project of Shaanxi Provincial Department of Education(20JY058)

OpenVX特征抽取函数在可编程并行架构的实现

张好聪¹^,⁺(), 李涛¹^,², 邢立冬¹, 潘风蕊¹

1.西安邮电大学电子工程学院,西安 710121
2.西安邮电大学计算机学院,西安 710121

作者简介:张好聪（1996—）,女,陕西渭南人,硕士研究生,主要研究方向为集成电路系统设计、数字图像处理。
ZHANG Haocong, born in 1996, M.S. candidate. Her research interests include integrated circuit system design and digital image processing.
李涛（1954—）,男,北京人,博士,教授,CCF会员,主要研究方向为集成电路系统设计、人工神经网络、机器学习。
LI Tao, born in 1954, Ph.D., professor, member of CCF. His research interests include integrated circuit system design, a.pngicial neural network and machine learning.
邢立冬（1980—）,男,山东潍坊人,博士,高级工程师,CCF会员,主要研究方向为集成电路系统设计、高速数字信号处理。
XING Lidong, born in 1980, Ph.D., senior engineer, member of CCF. His research interests include integrated circuit system design and high speed digital signal processing.
潘风蕊（1996—）,女,陕西渭南人,硕士研究生,主要研究方向为集成电路系统设计、数字图像处理。
PAN Fengrui, born in 1996, M.S. candidate. Her research interests include integrated circuit system design and digital image processing.
基金资助:
陕西省科技统筹项目(2015KTCQ013);陕西省教育厅协同创新中心项目(17JF032);陕西省教育厅科研计划项目(20JY058)

Abstract

Abstract:

Aiming at the mass computing and slow speed of serial structure calculation of digital image processing, parallel implementation of underlying feature extraction kernel functions in the latest open source OpenVX specification 1.3 is completed, and the verification is carried out with the self-designed OpenVX programmable parallel processor. In the underlying feature extraction of the image, the basic pixel processing function Color Convert, the local image processing functions Gaussian Filter and Median Filter of OpenVX specification 1.3 are selected for filtering and smoothing. Harris Corners and Canny Edge Detector are selected for feature extraction. By dividing the complex nodes with large amount of computation into several simple nodes, different graph execution models are constructed and mapped on the OpenVX parallel processor to realize image edge detection and feature point extraction respectively. Verilog is used to design the hardware circuit, and the FPGA chip xcvu440-flga-2892-2-e of Xilinx has comprehensively verified that, compared with the serial mapping structure, the parallel acceleration ratio of the selected kernel function on the OpenVX programmable parallel processor can be up to 14.269. Experimental results show that the kernel functions in OpenVX specification 1.3, especially the complex kernel functions, can achieve expected acceleration effect in this parallel processing structure, and the speedup ratio of parallel and serial structures increases linearly.

Key words: OpenVX specification 1.3, computer vision function, low level feature extraction, graph execution model, parallel processor

摘要：

针对数字图像处理计算量大、串行结构计算速度慢等特点,完成了最新的开源OpenVX计算机视觉加速规范1.3中底层特征抽取核函数的并行实现,使用自主设计的OpenVX可编程并行处理器进行了验证。在对图像的底层特征提取中,前期滤波及平滑处理选择OpenVX 规范1.3中基本像素点处理函数Color Convert（颜色转换）和局部图像处理函数Gaussian Filter（高斯滤波）、Median Filter（中值滤波）等,核心的特征抽取操作选择Harris Corners（哈里斯角点检测）和Canny Edge Detector（坎尼边缘检测）核函数,通过将计算量大的复杂结点拆分为多个简单结点,构建不同的基于图的执行模型,并映射在OpenVX并行处理器上,分别实现图像的边缘检测和特征点抽取。使用Verilog语言设计整体硬件电路,经Xilinx公司的FPGA芯片xcvu440-flga-2892-2-e综合验证,与串行映射结构相比,所选核函数在OpenVX可编程并行处理器上的并行加速比最高可达14.269。实验结果表明,OpenVX规范1.3中的核函数尤其是复杂核函数能够在本并行处理结构上达到预期的加速效果,且并行与串行结构加速比呈线性增长。

关键词: OpenVX规范1.3, 计算机视觉函数, 底层特征抽取, 图执行模型, 并行处理器

CLC Number:

TP302

ZHANG Haocong, LI Tao, XING Lidong, PAN Fengrui. Parallel Implementation of OpenVX Feature Extraction Functions in Programmable Processing Architecture[J]. Journal of Frontiers of Computer Science and Technology, 2022, 16(7): 1583-1593.

张好聪, 李涛, 邢立冬, 潘风蕊. OpenVX特征抽取函数在可编程并行架构的实现[J]. 计算机科学与探索, 2022, 16(7): 1583-1593.

Figures/Tables 21

Fig.1 HCCM topology

Fig.2 HCCM- and HCCM+ topology

Table 1 Parameters of HCCM, HCCM- and HCCM+

拓扑结构	直径	对分宽度
HCCM	$3 \times 2^{n - 1} - 2$	$2^{n}$
HCCM-	$2^{n} - 1$	4
HCCM+	$2^{n} - 1$	$2^{n} + 2$

Table 1 Parameters of HCCM, HCCM- and HCCM+

拓扑结构	直径	对分宽度
HCCM	$3 \times 2^{n - 1} - 2$	$2^{n}$
HCCM-	$2^{n} - 1$	4
HCCM+	$2^{n} - 1$	$2^{n} + 2$

Fig.3 OpenVX programmable parallel processor

Fig.4 Structure of PE

Fig.5 Example of graph execution model

Fig.6 Principle of Shift IP core of Xilinx

Fig.7 Optimized Median Filter

Fig.8 Label of current matrix pixel

Fig.9 Mapping of Gaussian Filter in PE

Fig.10 Optimized Canny Edge Detector graph execution model

Fig.11 Gradient direction division

Fig.12 Canny Edge Detector pipeline design

Fig.13 Canny Edge Detector mapping structure

Fig.14 Optimized Harris Corners graph execution model

Fig.15 Harris Corners pipeline design

Fig.16 Harris Corners mapping structure

Fig.17 Parallel speedup of OpenVX basic kernel functions

Fig.18 Speedup of OpenVX underlying feature extraction functions

Fig.19 Resource utilization

Fig.20 Original gray image and simulation results

References 19

[1]	The Khronos^® OpenVX Working Group. The OpenVX^TM specification[EB/OL]. (2020-09-10)[2020-10-05]. https://www.khronos.org/registry/OpenVX/specs/1.3/html/OpenVX_Specification_1_3.html.
[2]	马城城, 田泽, 黎小玉, 等. 统一渲染架构GPU图形处理量化性能模型研究[J]. 微电子技术, 2019, 45(2): 27-32.
	MA C C, TIAN Z, LI X Y, et al. Research on quantitative performance model of GPU graphics processing based on unified rendering architecture[J]. Application of Electronic Technique, 2019, 45(2): 27-32.
[3]	MOON C B, KIM B M, KIM D S. Real-time parallel image-processing scheme for a fire-control system[J]. IEIE Transactions on Smart Processing and Computing, 2019, 8(1): 27-35. DOI URL
[4]	KIY K I, ANOKHIN D A, PODOPROSVETOV A V. A software system for processing images with parallel computing[J]. Programming and Computer Software, 2020, 46(6): 406-417. DOI URL
[5]	LIU D. Embedded DSP processor design: application specific instruction set processors[M]. San Francisco: Morgan Kaufmann, 2008.
[6]	QI F. The building of interconnect structure and verification platform using Opnet[D]. Xi’an: Xi’an University of Posts & Telecommunications, 2012.
[7]	朱晓静, 胡伟武, 马可, 等. Xmesh: 一个mesh-like片上网络拓扑结构[J]. 软件学报, 2007, 18(9): 2194-2204.
	ZHU X J, HU W W, MA K, et al. Xmesh: a mesh-like topo-logy for network on chip[J]. Journal of Software, 2007, 18(9): 2194-2204. DOI URL
[8]	SMOLINSKI L, BARKALOV A, TITARENKO L. Adaptation of the two sources of code and one-hot encoding method for designing a model of microprogram control unit with output ide.pngication[J]. Intelligent Control and Automation, 2015, 6(2): 116-125. DOI URL
[9]	SHASHI P, SUCHITHRA R. Review study on digital image processing and segmentation[J]. American Journal of Computer Science and Technology, 2019, 2(4): 68. DOI URL
[10]	SALAMÍ E, VALERO M. A vector-µSIMD-VLIW architecture for multimedia applications[C]// Proceedings of the 34th International Conference on Parallel Processing, Oslo, Jun 14-17, 2005. Washington: IEEE Computer Society, 2005: 69-77.
[11]	BRILL F, GIDUTHURI R. The OpenVX^TM feature set definitions[R]. The Khronos^® OpenVX Working Group, 2021: 1-21.
[12]	HAN L, TIAN Y, Qi Q. Research on edge detection algorithm based on improved Sobel operator[J]. MATEC Web of Conferences, 2020, 309(1): 03031. DOI URL
[13]	JIANG J, LIU C, LING S. An FPGA implementation for real-time edge detection[J]. Journal of Real-Time Image Proces-sing, 2018, 15(4): 787-797.
[14]	WANG B B, XIANG Q. Fast median filter image processing algorithm and its FPGA implementation[J]. Frontiers in Signal Processing, 2020, 4(4): 88-94.
[15]	KRASNOPROSHIN V, MAZOUKA D. Graphics pipeline evolution based on object shaders[J]. Pattern Recognition and Image Analysis, 2020, 30(2): 192-202. DOI URL
[16]	闫小盼, 敖磊, 杨新. Harris角点检测的FPGA快速实现方法[J]. 计算机应用研究, 2017, 34(12): 3848-3851.
	YAN X P, AO L, YANG X. Real-time Harris corner detection method based on FPGA[J]. Application Research of Computers, 2017, 34(12): 3848-3851.
[17]	CAO J, CHEN L, WANG M, et al. Implementing a parallel image edge detection algorithm based on the Otsu-Canny operator on the Hadoop platform[J]. Computational Intelligence and Neuroscience, 2018, 3: 3598284.
[18]	SIKKA P, ASATI A R, SHEKHAR C. Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm[J]. Microprocessors and Microsystems, 2021, 80: 103514. DOI URL
[19]	李涛, 李雪丹. 基于PAAG的纹理特征提取算法的并行实现[J]. 西安邮电大学学报, 2015, 20(2): 11-15.
	LI T, LI X D. A parallel implementation of texture feature extraction algorithm based on PAAG[J]. Journal of Xi’an University of Posts & Telecommunications, 2015, 20(2): 11-15.

Parallel Implementation of OpenVX Feature Extraction Functions in Programmable Processing Architecture

OpenVX特征抽取函数在可编程并行架构的实现

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