Abstract: Traditional network-on-chip (NoC) uses metal links to connect routing nodes. The increase in IP cores on the chip not only leads to an increase in wiring complexity, but also leads to an increase in NoC transmission delay and power consumption. Due to the successful development of the micro antenna on the chip, the wireless com-munication within the chip is realized. Wireless communication has the characteristics of high bandwidth, low latency, and low power consumption, making the wireless network-on-chip (WNoC) an ideal alternative to traditional NoC, which can significantly improve system performance. Aiming at solving the problem of high energy consumption and delay caused by multi-hop communication between remote cores in the traditional large-scale network, this paper proposes an [8×8×4] 3D hybrid wireless network-on-chip architecture and a routing algorithm for this architecture. In addition, the problem of wireless node and wireless link placement in the topology design of hybrid WNoC has been discussed. The simulation results show that the deployment of wireless nodes in layer 0 and 3 has the best performance. Compared with the traditional network-on-chip structure, the topology proposed in this paper has greatly improved the average network delay and the total network power consumption.

Key words: wireless network-on-chip, topology, routing algorithm, wireless link placement, average delay, total power consumption

摘要： 传统的片上网络都是采用金属链路连接各个路由节点，芯片上IP核的增多一方面导致了布线复杂度的增加，另一方面也导致了片上网络传输延迟和功耗的增加。由于片上微型天线的成功研制，芯片内的无线通信得以实现。无线通信具有高带宽、低延迟、低功耗的特点，使得无线片上网络（WNoC）成为传统片上网络最理想的替代方案，可以显著提高系统的性能。针对传统大规模片上网络（NoC）远距离核间多跳通信所带来的高能耗与延时问题，提出了一种[8×8×4]的三维混合无线片上网络架构以及针对该架构的路由算法。此外，对在混合型无线片上网络的拓扑设计中所遇到的无线节点和无线链路放置等问题进行了讨论。仿真结果表明，将无线节点放在第0层和第3层所得到的性能最好，且该拓扑结构与传统片上网络结构相比，在网络平均延迟以及网络总功耗方面取得了很大的提升。

关键词: 无线片上网络, 拓扑结构, 路由算法, 无线链路放置, 平均延迟, 总功耗